The invention relates to a frequency synthesizer comprising a phase-locked loop having, in this order, at least a voltage-controlled oscillator (VCO), a first divider having an adjustable division factor n or n+1, wherein n is an integer, a second divider, the division factor of which is a programmable integer M, a phase comparator and a low-pass filter, the output signal, of this second divider and a reference signal, having a frequency F, being applied to said phase comparator for generating an output signal which is applied as control voltage to the voltage-controlled oscillator via the low-pass filter. This frequency synthesizer further comprises a first digital loop having a first pulse counter which counts the input pulses of the second divider and which is reset to its initial counting position by each output pulse of this second divider, and a first comparison device to which the counting position of the said first counter and a digital numerical value u, which is adjustable by means of a first adjusting device, are applied for generating a control signal for controlling said first divider so that the size of the frequency steps is equal to the reference frequency F, as well as a second digital loop having a second pulse counter counting the output pulses of said second divider and a second comparison device to which the counting position of said second pulse counter and a digital numerical value, which is adjustable by means of a second adjusting device, are applied for generating a control signal for controlling the first divider, so that the size of the frequency steps is equal to z, wherein z is smaller than F namely so that F is a multiple of z in order to realize a division into decimal fractions.
Frequency synthesizers of this type are used in practice for forming an oscillator frequency which is adjustable in elementary frequency steps and the accuracy of which is provided by a reference frequency which is preferably derived from a crystal-controlled oscillator. In the further course of the description the reference character f denotes the frequency value of the elementary step, that is to say the smallest frequency step obtainable in different synthesizers, which will be described hereinafter.
A frequency synthesizer consists basically of a phase-locked loop which comprises a fixed programmable divider provided between the oscillator and the phase comparator (the divider having a division factor N). In that case the elementary step f is equal to the reference frequency F (f=F). In such a synthesizer the natural cutoff frequency F.sub.cb of the loop (in the absence of the low-pass filter) is defined by the formula EQU f.sub.cb =K.phi.K.sub.o G/N (1)
where:
K.phi.: slope of the phase comparator in volts/rad. PA0 K.sub.o : slope of the oscillator in MHz/volts PA0 G: gain factor of the low-pass filter. PA0 N: total division ratio between the output of the oscillator and the input of the phase comparator (for all synthesizers described in this description).
In such a synthesizer the oscillator output frequency can be increased or decreased by one single elementary step by simply increasing or decreasing the adjusted value of the programmable divider by one.
Frequencies ranging from, for example, 200 MHz to 400 MHz can be generated, by means of a synthesizer of this type, in 100 kHz steps due to the provision of a programmable divider which is programmable between 2000 and 4000. After integration, the output signal of the phase comparator must be free from unwanted noise components which have a negative effect on the loop. To this end the low-pass filter must be dimensioned so that spurious signals which accompany the generated frequency are attenuated so that they are lower than the natural noise of the oscillator. Particularly the following relation must be satisfied: EQU F.sub.cf &lt;F (2)
On the other hand, in order to obtain a sufficiently rapid response of the loop, while the cutoff frequency of the low-pass filter, F.sub.cf, should not be too low, it must in any case exceed the natural cutoff frequency of the loop F.sub.cb in the absence of the filter in order to maintain a proper loop stability. Consequently, the following relation must be satisfied: EQU F.sub.cb &lt;F.sub.cf ( 3)
Combining the relation (2) and (3) results in the relation EQU F.sub.cb &lt;F.sub.cf &lt;F (4)
Therefore, the low-pass filter must have a cutoff frequency F.sub.cf which satisfies the above-mentioned relation (4). In addition, the cut-off frequency of the filter must be as high as possible in order to ensure that the hold range of the control loop is sufficiently large. So, for the above-mentioned digital example, a cut-off frequency of F.sub.cf =2 kHz. In case one wishes to increase the number of elementary steps by making the step size as small as possible it is necessary for this type of synthesizer to reduce the value F of the reference frequency proportionally and to increase the number of adjustable steps of the divider proportionally. Should one, for example, want a synthesizer of this type for generating frequencies from 200 MHz to 400 MHz in 50 kHz steps, the fixed divider must then be programmable between 4000 and 8000 and the reference frequency must be equal to 50 kHz. This manner of reducing the elementary step size has some limitations, resulting from the fact that the cut-off frequencies f.sub.cf and F.sub.cb must of course also be lower, which entails the above-mentioned drawbacks. From the above-mentioned formulae (1) and (4) it will namely be apparent that in the second digital example chosen above, the cut-off frequency of the filter must be reduced by 50%, that is to say to approximately 1 kHz.
By means of the known technique of division into decimal-fractions, it is, however, possible to mitigate the above-mentioned drawbacks by the provision of a digital loop which, in accordance with a predetermined rhythm, automatically acts on the programming of the divider or on the number of input pulses of this divider, so that the elementary step having frequency f is equal to a fraction of the reference frequency F. In contrast to the preceding case, this causes a slight variation in the time interval between the output pulses of the programmable divider, which variation is experienced as an interference at the output of the phase comparator but the advantageous result of the operation is that, for comparable output performances, a divider is obtained which is programmable with a smaller number of adjustable steps and a loop filter having a higher cut-off frequency, which results in an improved loop response and, consequently, in a more rapid control.
Such a synthesizer is known from, for example, French Pat. No. 1,556,495. By means of a synthesizer of this type it is, for example, possible to obtain frequencies by means of an oscillator which is adjustable between 200 MHz and 400 MHz, these frequencies varying in 100 kHz steps due to the provision of a divider, the division factor of which can be programmed between 200 and 400 a reference frequency of 1 MHz and a filter having a cut-off frequency at approximately 200 kHz, a result of which is a factor of 10 better than in the case considered earlier in this description. Let it now be assumed that N' is the desired number of megahertz, N' is equal to the value N to which the divider has been adjusted and that k is the desired integral number of elementary steps of 100 kHz (k.ltoreq.9). The second digital loop then acts in such a manner on the setting of the divider that in every 10 division cycles, that is to say after approximately 10 .mu.s, the divider has divided k times by N+1 and 10-k times by N, resulting in a frequency of: ##EQU1## The rhythm of the output pulse of the divider is equal to 1/10N+k, which results in a spurious signal having a frequency 100 kHz at the output of the phase comparator, which spurious frequency is located above the cut-off frequency of the filter, whereas the energy level of this spurious signal is sufficiently low to enable easy elimination by the filter. So this filter should have a cut-off frequency F.sub.cf which satisfies the relation: EQU F.sub.cf &lt;f (6)
and, by combining the relations (3) and (6) it also satisfies the relation: EQU F.sub.cb &lt;F.sub.cf &lt;f (7)
If an elementary step of 25 kHz is desired instead of a 100 kHz elementary step, in accordance with the technique of the decimal fraction principle, it is sufficient to include a modulo-40 counter in the digital loop instead of a modulo-10 counter. This would necessitate a considerable decrease of the cut-off frequency of the filter to below 25 kHz in order to enable the suppression of the spurious 25 kHz signal component to a sufficient extent, as is distinctly shown by formula (7).
An arrangement as described so far is suitable for frequency synthesis. Should it be desired to use such an arrangement as a phase or frequency modulator by, for example, varying the reference frequencies in the rhythm of the modulation, it appears that the maximum permissible rhythm of this modulation is limited to low values. Assuming the arrangement to operate with, for example, an elementary step of 25 kHz it then appears that the phase distortion produced in response to the modulation can only be kept within the permissible limits when the natural frequency of this modulation does not exceed the value of approximately F.sub.cb /3, for example, 5 k bits per second.